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| NCP5680 High Efficiency White LED Driver The NCP5680 product is a High Power charge pump driver dedicated to the recycling of a large Super Cap capacitor. The built-in DC/DC converter is based on a high efficient charge pump structure with 1X, 1.5X and 2X operating modes. It supports double power flash LED and torch operation. The controller is designed to properly drives large external NMOS device with accurate control of the peak current flowing into the LED. Also, the chip includes Open Load and Overload Detection circuit to protect the system against faults at Vout or LED level. Features http://onsemi.com UQFN24 MU SUFFIX CASE 523AG * * * * * * * * * * * * * * * * * * 2.7 to 5.5 V Input Voltage Range Dual Power Flash LED Capability Integrated Overload Protection Selectable Flash/Torch Mode of Operation Programmable SuperCAP Re-cycling Current Capable to Share the DC Voltage to Supply Peripheral Circuits Indicator LED Function Integrated Photo Sense Function Support Camera Strobe Built-in Short Circuit Protection Selectable Flash Time Out Safety Timing Support External NMOS up to 10 A Load Capability Embedded SuperCAP Vbias Fully I2C Protocol Compliant Support GSM Synchronization Built-in LED Test Function This is a Halide-Free Device This is a Pb-Free Device MARKING DIAGRAM 24 1 NCP 5680 ALYWG G NCP5680 = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) PIN CONNECTIONS PVba C1N C1P C2N C2P Vout VSD PHSEN SCL SDA TRIGFL NTC 1 PGND IsICH VgICH SCAP Vbias AGND Is2 Vgs2 Vds2 Vds1 Is1 Vgs1 (Top View) Typical Applications * Portable Photo Flash * Digital Cellular Phone Camera Photo Flash ORDERING INFORMATION Device NCP5680MUTXG Package Shipping UQFN24 3000 / Tape & Reel (Pb-Free) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. (c) Semiconductor Components Industries, LLC, 2009 May, 2009 - Rev. 0 1 Publication Order Number: NCP5680/D NCP5680 AUXILIARIES GND C4 0.22uF C2 C3 0.22uF 100uF GND C2N C2P NTGS3433 10uF 23 22 21 20 Q4 0.5R 19 C1N C1P Vout 2 17 24 R1 PVbat IsSCH C5 + 16 5 TRIGFL VgsSCH 3- TRIG 15 SCAP 1 14 3 SCL Vbias SCL GND 4 SDA 10 SDA Vds1 D1 1 VSD NTLJS4114 Q2 PWF3 PHOTO SENSE 12 Vgs1 R4 GND Q1 Is1 11 R2 100k 0.10R 2 PHSEN GND D2 Vds2 6 NTC 9 GND NTLJS4114 Q3 PWF3 NTC 8 13 Vgs2 R5 AGND Is2 GND GND PGND U1 7 0.10R 18 NCP5680 C1 +Vbat Figure 1. Typical Dual White LED Driver GND C1N Vbat 23 24 C1P C2N 22 21 C2P 20 19 18 GND Vreg TRIGFL SCL SDA GND R3 NTC VSD D1 PHOTO PHSEN R5 13 AGND GND Time Out OVLD2 WLED# = Flash Duration DLYLED# = Flash Delay FILED# = LED Peak Current WLED2 DLYLED2 FILED2 5 3 4 6 1 DIGITAL & ANALOG I2C CONTROL OVLD1 OVLD2 GND R R 14 SuperCAP Bias Vbat 10mA - 150mA GND OVER LOAD Vbias 3 + - I2C Cntl 17 Isp Re-charge Current 16 Control 15 IsSC SuperCAP Icharge Control VgsSC SCAP Q7 2 C1 0.5 Farad 1 Vout PGND R4 0.50 R CHARGE PUMP GND 2 OVLD1 WLED1 DLYLED1 FILED1 10 Vds1 Vgs1 Is1 LED#1 Iout Control 12 + - 11 Vbat 10mA - 150mA GND OVER LOAD Iout Control + - 9 8 7 Vds2 Vgs2 Is2 LED#2 Figure 2. Simplified Block Diagram http://onsemi.com 2 NCP5680 System Configuration Register CONFIG Indicator Register I-LED#1 ICON Thermal ShutDown TRIGFL SCL SDA DIGITAL CONTROL I2C Interface and Address Decoding TIMER CHARGE PUMP PHOTO SENSE Torch register I-LED#1 & 2 TILED Power Flash Register I-LED#1 FILED1 Power Flash Register Pulse Width WLED1 Power Flash Register Flash delay DLYLED1 Power Flash Register I-LED#2 FILED2 Power Flash Register Pulse Width WLED2 Power Flash Register Flash delay DLYLED3 ICON-Mode TORCH Mode FLASH Mode CHECK Mode CHECK Mode 5mA - 20mA ICON-Mode TILED 20mA - 100mA TORCH Mode + FLASH Mode TIME-OUT CHECK Mode TILED 20mA - 100mA TORCH Mode GND 9 Vds2 GND GND 10 Vds1 OVER LOAD 12 Iout Control 11 OVER LOAD Vgs1 Is1 8 FLASH Mode TIME-OUT Iout Control 7 Vgs2 Is2 Figure 3. Simplified NCP5680 Concept http://onsemi.com 3 NCP5680 PIN DESCRIPTIONS Pin 1 Name VSD Type OUTPUT, POWER Description This pin provides the 2.5 V Photo sense bias voltage. The bias voltage is connected when either a flash sequence has been selected, or the ENPH bit, in the CONFIG0 register, is set High. The output current is limited to 1 mA. The same pin is used to synchronize the charge pump operation by an external digital signal (see Figure 6). This pin fulfills two functions: PHOTO SENSE FUNCTION: the pin is connected to the external photo transistor. The operating voltage is limited in the 0 V to 1.7 V range. The voltage signal developed across that pin and ground during a flash sequence is compared with the PHREF voltage (encoded in one I2C data byte) to stop the flash pulse when the illumination is completed. This function is activated by the ENPH bit of the CONFIG0 register: ENPH = 0 the Photo sense is not activated, the flash time depends solely upon the TRIGFL pulse width, but is automatically limited by the Time out. ENPH = 1 the Photo sense is activated, the flash time depends upon the TRIGFL duration and the amount of light reflected by the scene, but limited by the Time Out. The PHREF reference is setup by the external MCU and stored into a built-in register through the I2C lines. CHARGE PUMP SYNC: the charge pump is de-activated when an external DC voltage (VMSK), in the 2.1 V to 2.5 V range, is applied to the PHSEN pin, whatever be the status of the photo sense transistor. The PHSEN resumes to the normal operation when the VMSK voltage is disconnected from the pin. This pin carries the I2C clock to control the DC/DC converter and to set up the output current. The SCL clock is associated with the SDA signal. This pin carries the data provided by the I2C protocol. A normal I2C sequence must send the I2C address plus a pair of SDA byte to properly program the embedded registers. This pin supports the digital signal coming from an external peripheral to trig the flash pulse. The duration of this positive pulse drives the LED, the photo sense being a way to accurately control the illumination of the scene. The TRIGFL signal is independent from the I2C interface, assuming the supercap has been properly charged to the appropriate voltage prior to launch the flash trigger. The built-in time out makes sure the flash duration does not extend the programmed limit (ranging from 2 ms to 200 ms). In addition, an internal pull-down resistor (100 kW typical) makes sure the pin is not floating when it is not connected to an external network. This pin monitors the external Negative Temperature Coefficient resistor. A programmable constant current is provided by the pin (10 mA typical) and the internal structure compares the resulting voltage against the programmed limit, the result being a stop of the power current when VNTC is lower than Vlimit. This pin, associated to Vgs2 and the Vout pin, returns the sense voltage, developed across the external shunt resistor, to the LED#2 current control loop. Care must be observed to avoid noise, stray capacitance and parasitic ohmic element between the shunt resistor and this point to minimize the parasitic pulses on the LED output current. This pin controls the gate of the external NMOS device and the LED is activated when the bit BLED1=1 in the Select Register byte. Care must be observed to minimize the routing between this pin and the gate of the external device. Similarly, the PCB track shall be designed to sustain the relative high current pulse flowing into the Ciss during the normal operation. The built-in driver structure is capable to control 10 A rated NMOS device with Ciss up to 2500 pF. This pin fulfils two functions: - support the I-LED when the Torch mode is activated. In this case, the Gate drive Vgs1 and Vgs2 signals are deactivated. The internal current mirror, programmed by the I2C port, limits the ILED1 to 100 mA maximum. - sense the Drain voltage across the external NMOS #2 to detect the overload condition: see Table 2. 2 PHSEN INPUT, ANALOG 3 4 5 SCL SDA TRIGFL INPUT, DIGITAL INPUT, DIGITAL INPUT, DIGITAL 6 NTC INPUT, ANALOG 7 Is2 INPUT, ANALOG 8 Vgs2 OUTPUT, POWER 9 Vds2 INPUT, ANALOG 1. Using low ESR ceramic capacitor, X5R type, is mandatory to optimize the Charge Pump efficiency and to reduce the EMI. Care must be observed to prevent large influence of the ceramic capacitor DC bias: using 10 V rated capacitor, 0805 or 0603 size, is recommended. 2. Total DC/DC output current is limited to 500 mA http://onsemi.com 4 NCP5680 PIN DESCRIPTIONS Pin 10 Name Vds1 Type INPUT, ANALOG Description This pin fulfils three functions: - support the I-LED when the Torch mode is activated. In this case, the Gate drive Vgs1and Vgs2 signals are deactivated. The internal current mirror, programmed by the I2C port, limits the ILED2 to 100 mA maximum - support the Indicator LED current when this mode is activated. In this case, the Vgs1 and Vgs2 signals are deactivated. The internal current mirror, programmed by the I2C port, limits the ILED1 to 20 mA maximum - sense the Drain voltage across the external NMOS #2 to detect the overload condition: see Table 2. This pin, associated to Vgs1 and the Vout pin, returns the sense voltage, developed across the external shunt resistor, to the LED#1 current control loop. Care must be observed to avoid noise, stray capacitance and parasitic ohmic element between shunt resistor and this point to minimize the parasitic pulses on the LED output current. This pin controls the gate of the external NMOS device and the LED is activated when the bit BLED0=1 in the Select Register byte. Care must be observed to minimize the routing between this pin and the gate of the external device. Similarly, the PCB track shall be designed to sustain the relative high current pulse flowing into the Ciss during the normal operation. The built-in driver structure is capable to control 10A rated NMOS device with Ciss up to 2500 pF. This pin carries the return to ground of the analog and digital blocks and must be connected to the external ground plane. This pin provides the bias voltage necessary to drive the supercap capacitor. The Vbias voltage is equal to Vout/2 and shall not be overloaded. This pin senses the voltage developed across the external SuperCAP. This voltage is fed back to the Vbias network to maintain the appropriate bias voltage at the superCAP mid point. This pin drives the gate of the external PMOS associated to the superCAP current control loop. Such a function might be omitted when not necessary in the final application. In this case, a direct contact can be set-up between the Vout pin and the external SuperCAP capacitor, the current being limited to 500 mA maximum. This pin, associated with the VgICH signal, is the return of the SuperCAP charge current sense. An external shunt resistor shall be connected between Vout and the external PMOS drain to monitor the superCAP charge current. These pins carry the ground return of the DC/DC converter and must be connected to the external ground plane. Since this pin provides the current charge path for the external Super Cap capacitor, cares must be observed to minimize both the ESR and the ESL parasitic elements between the Super cap negative electrode and these pins. Using ground plane technique is highly recommended. This pin provides the output voltage supplied by the DC/DC converter and must be bypassed by a 10 mF ceramic capacitor minimum located as close as possible to the pin. The circuit shall not operate without such bypass capacitor properly connected to the Vout pin. The converter supplies 500 mA maximum continuous current to total external load. Consequently, the re-cycling time depends upon the Super Cap capacitance value, the operating Vbat input supply voltage and the programmed IICH. The output voltage is internally clamped to 5.5 V maximum in the event of no load situation. On the other hand, the output current is limited to 100 mA (maximum) in the event of a short circuit to ground. One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C2N pin. One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C2P. One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C1N pin. One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C1P. This pin is connected to the input Battery voltage to supply all the built-in blocks. The pin must be connected to the Power plane and decoupled to ground by a 10 mF ceramic capacitor minimum. 11 Is1 INPUT, ANALOG 12 Vgs1 OUTPUT, POWER 13 14 15 16 AGND Vbias SCAP VgICH OUTPUT, POWER OUTPUT, Bias INPUT, ANALOG OUTPUT, ANALOG 17 IsICH INPUT, ANALOG OUTPUT, POWER 18 PGND 19 Vout OUTPUT, POWER 20 21 22 23 24 C2P C2N C1P C1N Vbat POWER POWER POWER POWER INPUT, POWER 1. Using low ESR ceramic capacitor, X5R type, is mandatory to optimize the Charge Pump efficiency and to reduce the EMI. Care must be observed to prevent large influence of the ceramic capacitor DC bias: using 10 V rated capacitor, 0805 or 0603 size, is recommended. 2. Total DC/DC output current is limited to 500 mA http://onsemi.com 5 NCP5680 MAXIMUM RATINGS (Note 3) Symbol VBAT Vout SCL, SDA, TRIGFL ESD PD Rqjc Rqja TA TJ TJmax Tstg Power Supply Output Power Supply Digital Input Voltage Digital Input Current Machine Model (Note 4) UQFN24 package - Power Dissipation @ TA = +85C (Note 5) UQFN24 package - Thermal Resistance Junction to Case UQFN24 package - Thermal Resistance Junction to Air Operating Ambient Temperature Range Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range Latch-up current maximum rating per JEDEC standard: JESD78. Rating Value -0.3 < Vbat < 7.0 6.0 -0.3 < V < VBAT 1 200 40 11 160 -40 to +85 -40 to +125 +150 -65 to + 150 100 Unit V V V mA V mW C/W C/W C C C C mA 3. Maximum electrical ratings define the values beyond which permanent damage(s) may occur internally to the chip whatever be the operating temperature 4. This device series contains ESD protection and exceeds the following tests: Standard ESD protections must be used when handling any integrated circuit. Appropriate ESD techniques must be observed to avoid damage to the device Machine Model (MM) 200V per JEDEC standard: JESD22-A115 5. The maximum package power dissipation limit must not be exceeded. 6. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J-STD-020A. http://onsemi.com 6 NCP5680 POWER SUPPLY SECTION: (Typical values are referenced to TA = +25C, Min & Max values are referenced -40C to +85C ambient temperature, unless otherwise noted), operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted. Pin 24 19 19 19 19 24 24 7, 11 9, 10 Symbol Vbat Iout IscL IscH Vout Tcy Istdb Iop IFTOL ITTOL Power Supply Continuous DC Current in the Load @ 3.0 V < Vbat < 3.2 V (Note 12) Continuous DC Current in the Load @ 3.6 V < Vbat < 5.5 V (Note 12) Continuous Output Short Circuit Current Output Voltage Regulation (4.5 V < Vout < 5.3 V) (See Table 5) DC/DC Re-Cycling Time (Cout = 0.50 Farad), Vbat = 4.2 V, IICH = 500 mA. From the end of the previous flash to the full load operation Stand By Current, Vbat = 3.6 V, Iout = 0 mA, DC/DC = Off, Vbias = Off Operating Current, @ Iout = 0 mA, Vbat = 3.6 V following a reset state Power Flash Output Current Tolerance: -25C < TA < 85C (Note 8) @Vbat = 3.8 V, ILED 500 mA (See Figure 10) Torch Output Current Tolerance I Torch @ Vds1 (Note 10) I Torch @ Vds2 (Note 10) Indicator LED Current - Indicator Mode @ Vds1 (Note 11) Clock Operating Frequency @ TA = 25C -5 -15 10 10 -25 0.1 0.85 1.0 0.6 +5 +15 100 100 +25 6.3 1.15 % mA mA % mA MHz -100 2 1.0 50 100 +100 Rating Min 2.7 Typ Max 5.5 220 400 Unit V mA mA mV s mA mA % 10 IIND Fpwr 7. The external shunt resistor shall be 1% tolerance or better 8. The external sense resistor shall be 1% tolerance or better 9. The maximum LED current depends upon the external NMOS device 10. The Vgs1 and Vgs2 pins are deactivated when the Torch mode is operating 11. The Vgs1 and Vgs2 pins are deactivated when the Indicator mode is operating 12. Parameter characterized, not tested in production, guaranteed by design. PROGRAMMABLE AND POWER UP PRESET CONDITION SECTION Pin 19 7, 11 7, 11 7, 11 Symbol IICH IFLSH Tpfl Tout Rating Programmable SuperCAP Re-Charge Current Range A 8% tolerance applies to each step of the five steps (Note 7) Programmable Flash Output Current Range (Note 8) See Figure 10 Programmable Power Flash Width Range Automatically Preset Power Flash Security Time Out @ Power Up Min 100 0.4 0.01 50 Typ Max 500 6.3 255 Unit mA A ms ms ANALOG SECTION: (Typical values are referenced to TA = +25C, Min & Max values are referenced -40C to +85C ambient temperature, unless otherwise noted), operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted. Pin 14 1 2 6 2 5 7, 11 Symbol Ibias VVSD VPHSEN VNTC VMSK RTRG Viref TSD TSDh Rating Super Cap Bias Voltage Current Capability (Vbias = VCC/2) Photo Sense Supply @ Iph = 2 mA Input Photo Sense Voltage Input Negative Coefficient Sensor Voltage (See NTCREG Register) Input Synchronization Transmit Mask Internal Pull-Down Resistor Input Voltage to Current Conversion across the Shunt Resistor during a Flash Sequence @ Rsense = 0.1 W (Notes 12 and 13) Thermal Shutdown Thermal Shutdown Hysteresis 95 2.1 100 100 145 20 105 Min 1.0 2.5 1.7 2.0 2.5 Typ Max Unit mA V V V V kW mV/A C C 13. The overall output current tolerance depends upon the accuracy of the external resistor. Using 1% or better resistor is recommended. http://onsemi.com 7 NCP5680 DIGITAL PARAMETERS SECTION (Typical values are referenced to TA = +25C, Min & Max values are referenced -40C to +85C ambient temperature, unless otherwise noted), operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted. Pin 3 3, 4 3, 4 Symbol FSCL VIH VIL Rating Input I2C Clock Frequency (Note 12) Positive going Input High Voltage Threshold, TRIGFL, SDA & SCL signals Negative going Input Low Voltage Threshold, TRIGFL, SDA & SCL signals 1.6 0 Min Typ Max 400 Vbat 0.4 Unit kHz V V 14. Maximum efficient power flash duration TFW depends upon the reservoir capacitor and the LED current. NOTE: Digital inputs undershoot < - 0.30 V to ground, Digital inputs overshoot < 0.30 V to Vbat REGISTER SELECTION BITS DEC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NOTE: HEX 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SDN Shut Down command CONFIG0 CONFIG1 register FILED1: set up the Power Flash LED1 FILED2: set up the Power Flash LED2 RFU TILED: set up the Video/Torch LED current (LED1 = LED2) FLDLY1: set up the time delay Start to LED1 FLDLY2: set up the time delay LED1 to LED2 RFU FLWID1: set up the Power Flash pulse width LED1 FLWID2: set up the Power Flash pulse width LED2 RFU PHSEN: set up the Photo sense range PHGAIN: set up the input amplifier gain VOUTREG: set up the Vout voltage INMDE: set up the Indicator mode (ICON) NTCREG: set up the NTC low limit NTCBIAS: set up the DC bias current to NTC ICHG: set up the superCAP re-charge current TOUT: set up the Power flash time out RFU RFU STATUS RFU Reserved for manufacturing test: do not access All register addresses beyond $18 are reserved for ON Semiconductor manufacturing tests and shall not be R/W in the application. http://onsemi.com 8 NCP5680 $00 - SDN Shut Down command $01 - CONFIG0 $02 - CONFIG1 register $03 - FILED1 : set up the Power Flash LED1 $04 - FILED2 : set up the Power Flash LED2 $06 - TILED : set up the Video/Torch LED current $07 - FLDLY1: set up the time delay Start to LED1 $08 - FLDLY2 : set up the time delay Start to LED2 $0A - FLWID1: set up the Power Flash pulse width LED1 $0B - FLWID2: set up the Power Flash pulse width LED2 $0D - PHSEN: set up the Photo sense range $0E - PHGAIN : set up the input amplifier gain $0F - VOUTREG: set up the Vout voltage $10 - INMDE: set up the Indicator mode (ICON ) $11 - NTCREG : set up the NTC low limit $12 - NTCBIAS : set up the DC bias current to NTC $13 - ICHG: set up the superCAP re-charge current $14 - TOUT : set up the Power flash time out $17 - STATUS Shutdown RESET Set Pre Charge Set Charge Pump Set Vout SetUp ICHG superCAP Set up the NTC bias current Set up the NTC reference voltage Enable/Disable the NTC function Select Flash mode Select Torch/Video mode Select Indicator/Icon mode SetUp ILED indicator SetUp IFLASH#1 SetUp IFLASH#2 Enable LED#1 Enable LED#2 Set Time Out Set Pulse Width LED#1 Set Pulse Width LED#2 Set Delay Flash LED#1 Set Delay Flash LED#2 Set Flash Trigger :I2C/External SetUp ITORCH Activate/Deactivate Photo Sense SetUp Photo Sense Refrence SetUp Check Sequence Read STATUS register X X X X X X X X X X X X X X X X X X X X X X X X X X X FUNCTIONS PROGRAMMING REGISTERS X COMMENTS send %0000 0000 send % 1xxx xxxx send %xxxx xx1x send %xxxx x1xx send %0000 0000 to %0000 0111 send %0000 0000 to %0000 0111 send %0000 0000 to %0011 1111 send %0000 0000 to %0001 1111 send % xx1x xxxx send % xx1x xxx0 send % xx0x xxx0 send % xx0x xxx1 send %0000 0000 to %0011 1111 send %0000 0000 to %0011 1111 send %0000 0000 to %0011 1111 send % xxxx xxx1 send % xxxx xx1x send %0000 0000 to %0111 1111 send %0000 0000 to %1111 1111 send %0000 0000 to %1111 1111 send %0000 0000 to %1111 1111 send %0000 0000 to %1111 1111 Send % xxx1 xxxx send %0000 0000 to %0011 1111 Send% xxx1 xxxx send %0000 0000 to %1111 1111 Table 1. Functions Programming Table INTERNAL REGISTERS DESCRIPTION SDN[7..0] Shut Down command $00 B7 RESET 0 B6 0 B5 0 B4 0 B3 0 B2 0 B1 0 B0 0 SDN[7:0] = NCP5680 is in Shut Down mode, all the LED are switched to the OFF state, the previously programmed parameters are stored into their respective registers. The Vout voltage is no longer controlled by the chip and the SuperCap is disconnected from the Vbat. The SuperCap voltage bias is maintained until the Vout voltage is below 2 V. CONFIG0[7..0] Configuration register $01 B7 TPLGT RESET 0 B6 ENTC 0 B5 ICHG 0 B4 ENPH 0 Although the third byte could carry any data when an SDN command is transmitted, it is preferred to force all the 8 bits to zero. Consequently, a typical shut down command shall be: $I2C Address - $00 - $00. Note: there is no internal structure to rapidly discharge the SuperCap: it is up to the external circuit to take whatever action is necessary to cope with the end application. B3 CKPLS 0 B2 CKPRC 0 B1 BKL2 0 B0 BKL1 0 TPLGT: activate the 200 ms time out associated to the Picture Light function. TPLGT = 0 the 200 ms is de-activated TPLGT = 1 the 200 ms time out is activated and apply to the Picture Light only. Note: the 200 ms time out is automatically asserted when the TILED current is higher than 100 mA. http://onsemi.com 9 NCP5680 ENTC: control the NTC input function ENTC = 0 the external NTC is de-activated and no action is forwarded to the Power Flash current block. ENTC = 1 the external NTC is biased by the internal current and the Power flash current is switched OFF when the NTC drops below the minimum level defined by the NTCREG register ICHG: control the superCAP charging current during a start up sequence ICHG = 0 the charging current is limited to 250 mA maximum (125 mA typical) ICHG = 1 the charging current is limited to 350 mA maximum (250 mA typical) ENPH: control the photo sense ENPH = 0 the photo sense is de-activated ENPH = 1 the photo sense is activated CONFIG1[7..0] Configuration register $02 B7 RESET RESET 0 B6 CPFL 0 B5 SELFL 0 B4 CKPLS: this bit controls the LED1 & LED2 internal check during a flash sequence CKPLS = 0 no LED check performed during a flash sequence CKPRC = 1 the LED check are automatically performed, during a flash sequence, the results can be read from the STATUS register. If a fault is detected at any time during a flash pulse, the flash sequence is immediately stopped. CKPRC: this bit controls the LED1 & LED2 internal check out of a flash sequence. CKPRC = 0 no LED check performed CKPRC = 1 the LED check are automatically performed (both LED1 and LED2), the results can be read from the STATUS register. BKL1: = LED2 control BKL = 0 LED2 de-activated BKL = 1 LED2 activated BKL0: = LED1 control BKL = 0 LED1 de-activated BKL = 1 LED1 activated B3 EXTRG 0 B2 CPACT 0 B1 SACT 0 B0 ENIND 0 I2CTRG 0 RESET: B7 = 1 unconditionally clear all the registers to their respective zero state. CPFL: of the Flash Pulse being identical to the TRGFL pulse width. The Time out is activated. The two LED are simultaneously powered, unless one of the two LED is not activated, according to the CONFIG0 register setup. CPACT: B6 = 0 the charge pump is de-activated when a power flash sequence is on going B6 = 1 the charge pump is fully active during a power flash sequence. SELFL: B5 = 0 the Torch / Video mode is engaged, the flash cannot be fired, the ILED current is limited to 100 mA/LED. B5 = 1 the Flash mode is engaged, the flash can be fired. I2CTRG: B2 = 0 the charge pump is de-activated B2 = 1 the NCP5680 and the Charge Pump are active. The Vout voltage is equal to the programmed value stored into VOUTREG register. All the LED are biased as defined in the previous or next programming sequence. A flash can be launched. SACT: B4 = 0 when an I2C flash sequence is on going, the flash is immediately stopped by this I2C command. B4 = 1 The flash is immediately launched by the I2C when this bit is High, unless the EXTRG bit is high. In this case, the external Trigger pulse has the highest priority. EXTRG: B3 = 0 The TRGFL pin is de-activated, the flash can be launched by the I2C port only B3 = 1 The Photo Flash sequence is activated by the positive going pulse applied to the TRGFL pin, the duration B1 = 0 the NCP5680 is active, but the pre-charge is de-activated. If the CPACT is Low, the Vout voltage will be low. If the CPACT bit is High, then the Vout voltage will be equal to the programmed value. B1 = 1 the NCP5680 is active, the pre-charge is activated. The Vout voltage is equal to the Vbat voltage, unless the Charge pump is activated (CPACT = 1). All the LED are biased as defined in the previous or next programming sequence. A power limited flash can be launched. ENIND: B0 = 0 the Indicator function is de-activated B0 = 1 the Indicator function is activated. http://onsemi.com 10 NCP5680 FILED1[7..0] Power Flash LED1 ILED register $03 B7 mA RESET 0 0 B6 0 0 B5 3200 0 B4 1600 0 B3 800 0 B2 400 0 B1 200 0 B0 100 0 FILED2 [7..0] Power Flash LED2 ILED register $04 B7 mA RESET 0 0 B6 0 0 B5 3200 0 B4 1600 0 B3 800 0 B2 400 0 B1 200 0 B0 100 0 TILED [7..0] Torch / Video / Picture View/ View Finder LED1 & LED2 register $06 B7 mA RESET NOTE: 0 0 B6 128 0 B5 64 0 B4 32 0 B3 16 0 B2 8 0 B1 4 0 B0 2 0 The 200 ms time out is automatically asserted when TILED is higher than 100 mA. The TILED current is maintained constant when TILED is equal or lower than 100 mA. FLDLY1[7..0] Power flash Delay #1 register $07 B7 ms RESET NOTE: 256 0 B6 128 0 B5 64 0 B4 32 0 B3 16 0 B2 8 0 B1 4 0 B0 2 0 Tolerance of the Fpwr Clock parameter applies to the timing parameters. FLDLY2[7..0] Power flash Delay #2 register $08 B7 ms RESET NOTE: 256 0 B6 128 0 B5 64 0 B4 32 0 B3 16 0 B2 8 0 B1 4 0 B0 2 0 Tolerance of the Fpwr Clock parameter applies to the timing parameters. FLWID1[7..0] Power flash LED1 width register $0A B7 ms RESET NOTE: 128 0 B6 64 0 B5 32 0 B4 16 0 B3 8 0 B2 4 0 B1 2 0 B0 1 0 Tolerance of the Fpwr Clock parameter applies to the timing parameters. FLWID2[7..0] Power flash LED2 width register $0B B7 ms RESET NOTE: 128 0 B6 64 0 B5 32 0 B4 16 0 B3 8 0 B2 4 0 B1 2 0 B0 1 0 Tolerance of the Fpwr Clock parameter applies to the timing parameters. PHSEN[7..0] Photo Sense Reference register $0D B7 mV RESET NOTE: 1280 0 B6 640 0 B5 320 0 B4 160 0 B3 80 0 B2 40 0 B1 20 0 B0 10 0 a 12.5% tolerance applies to each bit of the PHSEN register PHGAIN[7..0] Photo Sense Input Amplifier gain register $0E B7 gain RESET NOTE: 0 0 B6 8 0 B5 4 0 B4 2 0 B3 1 0 B2 0.5 0 B1 0.25 0 B0 0.125 0 a 10% tolerance applies to each bit of the PHGAIN register http://onsemi.com 11 NCP5680 VOUTREG[7..0] Vout Adjustment register $0F B7 mV RESET NOTE: 0 0 B6 0 0 B5 0 0 B4 0 0 B3 0 0 B2 800 0 B1 400 0 B0 200 0 The Vout voltage must be reduced to the minimum value when the Torch/Video mode is activated: see the Torch/Video paragraph and the Thermal Consideration note. INMDE[7..0] Indicator mode register $10 B7 mA RESET 0 0 B6 0 0 B5 3200 0 B4 1600 0 B3 800 0 B2 400 0 B1 200 0 B0 100 0 NTCREG[7..0] External NTC low limit register $11 B7 mV RESET CNTC 0 B6 0 0 B5 0 0 B4 1600 0 B3 800 0 B2 400 0 B1 200 0 B0 100 0 CNTC: a positive going pulse clears the NTC high temperature limit and clear the STATUS[NTC] bit. The bit shall be Low to resume NTC normal operation. NOTE: a 15% tolerance applies to each bit of the NTCREG register NTCBIAS[7..0] NTC current bias register $12 B7 mA RESET NOTE: 0 0 B6 0 0 B5 320 0 B4 160 0 B3 80 0 B2 40 0 B1 20 0 B0 10 0 a 10% tolerance, measured at Vbat = 3.6 V, applies to each bit of the NTCBIAS register ICHG[7..0] SuperCAP re-charge current register $13 B7 TOUTDIS2 RESET NOTE: 0 B6 TOUTDIS1 0 B5 0 0 B4 0 0 B3 0 0 B2 400 mA 0 B1 200 mA 0 B0 100 mA 0 TOUTDIS1 & TOUTDIS2: these two bits are used to disconnect the Time Out function when B7 and B6 are High: TOUTDIS1 & TOUTDIS2: B7 or B6 = 0 --> the Time Out function is active and operate normally. TOUTDIS1 & TOUTDIS2: B7 = B6 = 1 --> the Time Out function is de-activated STATUS[7..0] System LED check READ register $17 B7 0 READ only RDY B6 0 NTC B5 0 0 B4 SLED2 0 B3 SLED1 0 B2 RFU 0 B1 VDS2 0 B0 VDS1 0 RDY: Output Capacitor status: 0 Output capacitor not fully charged yet 1 Output capacitor fully charged to the programmed voltage NTC: external thermal sensor flag 0 a high temperature has been sensed by the NTC. All the power blocks are de-activated (Charge pump, flash and Torch/Video) 1 normal operation, no high temperature detected. B5 = RFU SLED2: LED#2 Check 0 LED#2 A/K Short Circuited 1 Pin OK SLED1: LED#1 Check 0 LED#1 A/K Short Circuited 1 Pin OK B2 = RFU VDS2: LED#2 Check 0 Pin connection or LED#2 OPEN 1 Pin OK VDS1: LED#1 Check 0 Pin connection or LED#1 OPEN 1 Pin OK http://onsemi.com 12 NCP5680 TOUT[7..0] Time Out register $14 B7 ms RESET NOTE: 256 0 B6 128 0 B5 64 0 B4 32 1 B3 16 1 B2 8 0 B1 4 0 B0 2 1 The minimum time out is preset at 50 ms. Tolerance of the Fpwr Clock parameter applies to the timing parameters. "The Time Out function can be de-activated to generate the infinite operation requested by the Video mode. To achieve such a function, the here below logic conditions must be met: - ICHG register: bits B7 = B6 = 1 - CONFIG1 register: bit B3 = 1 (external trigger flash only) - FILED1 and FILED2 must be lower or equal to 500 mA each The Time out is maintained is any of the three conditions is not fulfilled." DC/DC Operation The converter is based on a charge pump technique to generate a constant DC voltage capable to either re-charge the external Super Cap, or to drive the LED in the torch mode. The system regulates the current flowing into the LED by means of an internal current mirror associated with the external shunt resistor and the external power NMOS. The output voltage is adjusted and regulated in the range 4.5 V to 5.5 V across the external Super Cap reservoir, the NMOS device being used as a current controlled source to drive the LED. When the DC/DC is not active, the voltage across the external reservoir capacitor is either zero or equal to the voltage present at the Vbat pin, depending upon the operation defined by the SACT bit in the CONFIG1 register. The output current is setup by the external reference resistor connected between Vout and the LED. With a 100 mV drop across the shunt resistor, the forward current into the LED being: ILed = 0.10/R. The shunt resistor must be sized to sustain the amount of current flowing during the operation. The Vout voltage is continuously monitored and the charge pump stops when the voltage is above the maximum programmed value. The converter resumes to normal operation when the voltage drops below the programmed value (there is no fault latched since the converter operates in the hysteretic regulation mode). Consequently, the chip can operate under no load conditions during any test procedures with no risk in term of OVP situation. However, when the check routine is activated, the voltage present at the drain of the external NMOS is monitored to detect fault condition that might develop in Figure 4. Typical Pre Charge Sequence the power flash structure according to Table 2. Table 2. LED Drive Overload Detection Conditions Vds 0V 0V 0 V < Vds < Vout = Vout > 2.0 V NCP5680 status Standby Pulsed Flash Standby Standby Pulsed Flash Fault LED open or Cathode to ground shorted LED open or Cathode to ground shorted Normal operation, no fault Anode to Cathode LED shorted Anode to Cathode LED shorted, Charge pump de-activated, flash de-activated When the check routine is activated, the result is stored into the STATUS register and can be read back by the I2C port. On the other hand, the external SuperCAP re-charge current can be programmed, through the I2C port, to better handle the total energy demand. The three bits present in the ICHG register makes possible the adjustment of the re-charge current from 100 mA to 500 mA, keeping in mind that the charge pump is designed to supply up to 500 mA maximum. http://onsemi.com 13 NCP5680 Finally, the charge pump can be de-activated, upon command from the MCU, during a transmit burst pulse applied to the PHSEN pin: see typical schematic Figure 6. In this case, any on going flash keeps going, but no energy is absorbed from the battery as depicted in Figures 7 and 8. Similarly, the burst function can be used to smooth the input battery current as depicted in Figure 9. R2 470k 6 U2 NTJD1155L 15 TXMSK GND 4 D1 PHOTO VSD NCP5680 PHSEN R1 22k GND 23 Figure 5. Typical Pre Charge and Full Charge Sequence TX Mask = 1 Figure 6. Typical Transmit Burst Mask Figure 7. GSM Burst during the Re-charge of the SuperCAP Figure 8. GSM Burst during a Flash and Re-charge Sequence Figure 9. GSM Active during a Re-charge Cycle http://onsemi.com 14 NCP5680 From Charge Pump Vref FAULT FLASH LED VIDEO/TORCH Ref Current Vdsx Vbias Vout Vout 2 + 3 BAL - 1.2F 1 GND GND Q21 Supercap-XX Vgsx NTMS4N01R 1 +2 1.2F 5.5V Bal. 3 VCC 2 FILEDx REF-SEL 3 7 4 GND 6 3 2 VCC 7 4 GND VCC 6 7 4 GND 3 2 GND GND GND Isx 6 GND 0.1R Figure 10. Basic Output Power flash Current Regulation Structure with Video/Torch loop and Overload detection Table 3. Recommended SuperCAP Products Manufacturer CAP-XX CAP-XX CAP-XX TDK TDK HA230F HW207F HS206F EDLC122344-551-2F-30(E) EDLC272020-501-2F-50(E) Part Number Table 4. Maximum External MOS Transistor Input Capacitance CcissN CcgdN CcissP External NMOS input capacitance External NMOS Gate / Drain capacitance External PMOS input capacitance TBD TBD 2500 TBD 2500 pF pF pF Output Voltage Regulation The output voltage -Vout- can be adjusted by the I2C port within the 4.5 V to 5.5 V range (200 mV/step), as depicted in Table 5. It is preset at 4.5 V upon a Power On Reset or a RESET command. Table 5. Output Voltage Adjustment B7 0 0 0 0 0 0 B6 0 0 0 0 0 0 B5 0 0 0 0 0 0 B4 0 0 0 0 0 0 B3 0 0 0 0 0 0 B2 0 0 0 0 1 1 B1 0 0 1 1 0 0 B0 0 1 0 1 0 1 Vout 4.5 V 4.7 V 4.9 V 5.1 V 5.3 V 5.5 V http://onsemi.com 15 NCP5680 Load Connection The primary function of the NCP5680 chip is to control two high power LED arranged in the photo flash structure. The LED are independently activated or de-activated by means of the I2C command. In addition, the chip is capable to drive the Torch mode or the Indicator function, the output LED current being monitored by the associated current mirrors. Although it is possible to connect several LED in parallel to share the output current, such solution is discouraged since the matching between the LED can no longer be guaranteed. However, using a dual NMOS device in the same package provides a way to drive up to four LEDs with full flash current capability per LED, as depicted in Figure 11. LED Programming Operation All the electrical biases of each LED are set up by means of an hexadecimal byte coming from the I2C port. The Iout peak current, the flash pulse duration and the flash delays are stored into registers associated to each LED. Consequently, each LED can have a different amplitude, duration and delay during a single photo flash sequence. The mode of operation - either Video torch or Flash, or Picture Light or ICON - is selected by the I2C command. In addition, the photo flash sequence can be activated either by the appropriate I2C command, or by means of the dedicated TRGFL pin, assuming the chip has been previously activated (the TRGFL signal has no effect if NCP5680 is in shut down mode). The Time out is automatically asserted when a pulsed flash is activated. Power Flash The I-LED flash current is regulated by means of the analog loop built with the external NMOS device TFW 10 ms TRIGFL FLASH PHOTO SENSE Mode PHOTO SENSE Feedback Charge Pump Active Standby Re-cycle: 2sec @ Cout = 1F, Vbat = 4V associated to the external shunt resistor: see Figure 10. The internal operational amplifier uses the reference voltages, as defined by the contain of register FILED1 and FILED2, to monitor the current flowing in the loop. Basically, the Voltage to current ratio is 100 mV/A: a 100 mW resistor will force a 1 A I-LED current with 100 mV programmed at the FILED1 or FILED2 register. Of course, different value for the shunt resistor can be implemented, but care must be observed as it might be difficult to extract a low drop voltage in a noisy environment. The power flash sequence can be activated in two ways: 1. Using the I2C command associated to the CONFIG1register: the positive going of the bit I2CTRG signal fires the pulsed flash (the pulse width depends upon the contain of FLWID1 & FLWID2 registers), the delays are activated, depending upon the contain of FLDY1 & FLDY2 registers, the time out is engaged, the output current is forced to the values previously stored into the FILED1 and FILED2 registers. The flash can be as short as 100 ms, with 255 ms as a maximum duration (see TOUT register). The I2CTRG bit in the CONFIG1 register is automatically reset to Low when the flash pulse is completed. 2. Using a direct command through the TRGFL pin, assuming the EXTRG bit in the CONFIG1 register is set to High. In this case, the time out is activated but the timers and the pulse width registers are de-activated since the duration of the pulsed flash depends solely upon the duration of the signal present at the TRGFL pin. TRIGFL Pulse TFW Photo sense function activated Illumination level is preset by the I2C previous message Photo sense feedback Figure 11. Basic Operation Timings http://onsemi.com 16 NCP5680 Select FlashTrigger CONFIG1[EXTRG) Set I2CTRIG Set TimeOut Send EXTLTRIGGER Read Flash Pulse The Flash duration is setup by the I2C FLWIDx register I2C TRIGGER Selected External Trigger Selected I2C TRIGGER Selected The Flash duration is equal to the EXTL TRIGGER Pulse width The Flash is switched OFF by the Time Out control Figure 12. Flash Mode of Operation Flash Configuration When the power flash is activated, the default Time out is preset to 50 ms typical and can be set up to a different timing through an I2C command. Although the NCP5680 can sustain a 255 ms time out, care must be observed, at system level, that both the external NMOS transistors and the LED are capable to absorb the increase of temperature coming from the extra heat developed during a larger time out sequence. LED Flash Current @ Vbat=3.6V LED1 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 LED2 V_Is(mV) To generate a flash pulse, several registers must be preset before a flash takes place: FILED1 = $03 LED1 set up the peak current FILED1 = $04 LED2 set up the peak current FLDLY1 = $07 LED1 set up the delay time FLDLY2 = $08 LED2 set up the delay time FLWID1 = $0A LED1 set up the pulse width time FLWID2 = $0B LED2 set up the pulse width time VOUTREG = $0F set up the output voltage value TOUT = $14 set up the time out A typical sequence is depicted here below: - Set up the configuration registers to control the flash sequence - Set up the pulse width, the amplitude and the delay time 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 FILED(A) Figure 13. Flash ILED Current vs. Vsense CONFIG0 Select the Photo Sense Mode of Operation Select the Automatic LED check during a pulse Select LED2 Select LED1 B7 - - - - B6 - - - - B5 1/0 - - - B4 - 1/0 - - B3 - - - - B2 - - - - B1 - - 1/0 - B0 - - - 1/0 Typical Sequence: - send the I2C address - select the CONFIG0 register - activate LED1 and LED2 $7C $01 $03 http://onsemi.com 17 NCP5680 CONFIG1 Select the Charge Pump Mode of Operation: 0 charge pump de-activated during a flash pulse 1 charge pump activated during a flash pulse Select the Flash mode Control a flash sequence from the I2C port: 0 the I2C trigger is de-activated, clear previous sequence 1 the I2C trigger is activated and the flash pulse is forced on the positive going pulse Control the charge pump: 0 charge pump de-activated 1 charge pump activated Control the pre charge mode: 0 pre charge pump de-activated 1 pre charge pump activated B7 - B6 1/0 B5 - B4 - B3 - B2 - B1 - B0 - - - - - 1 - - 1/0 - - - - - - - - - - - - - 1/0 - - - - - - - - 1/0 - Typical Sequence: - send the I2C address $7C - setup the Output Voltage $0F, $xx - setup the LED1 current amplitude $03, $xx - setup the LED1 pulse width $0A,$xx - setup the LED1 delay $07, $xx - send the I2C address $7C - setup the LED2 current amplitude $04, $xx - setup the LED2 pulse width $0B, $xx - setup the LED2 delay $08, $xx - send the I2C address $7C - select the CONFIG1 register $02 - Activate the charge pump during a flash pulse & %0110 0110 Activate the charge pump & Select the flash Mode & Clear previous sequence - send the I2C address $7C - select the CONFIG1 register $02 - Activate the charge pump during a flash pulse & %0111 0110 Activate the charge pump & Select the flash Mode & Send I2C Flash trigger Figure 14. Typical Flash Pulses Sequence Figure 15. Typical Flash Pulses with 2A peak in LED2 http://onsemi.com 18 NCP5680 Figure 16. Typical Flash pulse with Time Out Engaged Figure 17. Typical ILED Rise & Fall Time Torch / Video The torch/video mode is activated when the SELFL bit is low. In this case, the pulse width and delays registers are irrelevant, the time out is de-activated. The output current is setup by the contain of the TILED register. In addition, the time out is immediately activated if the contain of the TILED register exceeds $3F. Similarly, the external NMOS are deactivated (Vgs1 = Vgs2 = 0) and the ILED current is controlled by the built-in current mirrors, the maximum current being 100 mA per LED. Figure 18. Basic Low Power Current Mirror Structure http://onsemi.com 19 NCP5680 Auxiliary Operation The power capability of the built-in charge pump makes possible the use of a permanent load connected at the Vout pin with a 100 mA continuous load current. Two situations shall be considered: a - the auxiliary load is ripple sensitive and fully active when the power flash is triggered: using the extra PMOS transistor is mandatory to isolate the auxiliary load from the power LED. In this case, a minimum 100 mF/6.3 V capacitor is required to maintain the Vout voltage constant during the operation. b - the auxiliary load is de-activated during a flash sequence : using the PMOS transistor is not mandatory and the auxiliary can be powered from the SuperCAP. Thermal Consideration Based on the data sheet published by the LED manufacturers', the forward drop of these LED can be 3 V or less when the forward current is 100 mA and below. Assuming that such a device is connected in the system, a relative large amount of power will be dissipated into the current mirrors built inside the NCP5680. Let assume that Vf = 3.0 V @ If = 100 mA and consider the Vout was programmed at 5.5 V. The voltage across the current mirror will be: Vom = Vout - Vf Vom = 5.5 - 3 = 2.5 V The power dissipated into the current mirror will be Pom = Vom * If Pom = 2.5 * 0.1 = 0.25 W Assuming that the two LED are activated simultaneously, the total power dissipated by the current mirror will be 0.50 W. In addition, the charge pump is active during this operation to maintain Vout at the programmed value, and an extra 400 mW will be added to the losses. On the other hand, it is unlikely possible to increase the PCB area large enough to significantly reduce the thermal resistance between the QFN package and the ambient air: generally speaking, the Rthj-a is in the range of 40C/W, assuming the Rthj-c negligible in comparison to the Rthc-a. Taking all these parameters into account, the die temperature can be calculated : DTj = SP x Rthj-c DTj = (0.5 +0.4)*40 = 36C Assuming that the system operates under +85C ambient temperature, then the chip will be at 85+36 = 121C, very close to the maximum rating. To avoid any long term fault with the system, it is strongly recommended to reduce the Vout voltage to the minimum value when the Torch/Video mode is activated. In this case, the net voltage across the current mirror will be limited to 4.5 - 3.0 = 1.5 V, the losses will decrease accordingly, yielding a 113C maximum junction temperature under the same environment as depicted before. To control the Torch/Video mode, several registers must be preset before a flash takes place. A typical sequence is depicted here: CONFIG0 Select LED2 Select LED1 B7 - - B6 - - B5 - - B4 - - B3 - - B2 - - B1 1/0 - B0 - 1/0 Typical Sequence: - send the I2C address - select the CONFIG0 register - activate LED1 and LED2 $7C $01 $03 B7 - B6 1 B5 - B4 - B3 - B2 - B1 - B0 - CONFIG1 Select the Charge Pump Mode of Operation: 0 charge pump de-activated during a flash pulse 1 charge pump activated during a flash pulse Select the Torch/Video mode Control the charge pump: 0 charge pump de-activated Control the charge pump: 1 charge pump activated Control the pre charge mode: 0 pre charge pump de-activated Control the pre charge mode: 1 pre charge pump activated - - - - - - 0 - - - - - - - - - 1 - - - 1 - - - Indicator The indicator mode is activated when the ENIND bit in the CONFIG1 register is High. The pulse width and timer registers are irrelevant, the time out is de-activated. The indicator function applies solely to LED 1. The Torch/ Video mode is bypassed if it was active in the previous phase and resumes to the previous situation when ENIND = Low. The external NMOS are deactivated (Vgs1 = Vgs2 = 0) and the ILED current is controlled by the built-in current mirror, the maximum current being 6.3 mA. The indicator might be activated permanently, both the power flash or the video/torch mode having an automatic highest priority: the indicator current for LED1 is summed with the main current coming from either the flash or the video/torch circuits. http://onsemi.com 20 NCP5680 Photo Sense When the photo sense is activated (bit PHEN = 1 in the CONFIG0 register), the duration of the flash is automatically reduced when enough light back from the photo target is sensed through the external sensor. The analog signal present at the PHSEN pin is amplified (depending upon the gain setup by the MCU) and compared with the reference programmed by the MCU: the photo flash pulse is switched OFF when the input signal is higher than the content of the PHSEN register (see Figure 19). The built-in flip flop makes sure that a single pulse is generated when the light feedback has been acknowledged by the sensor. The flip flop is reset to the armed position upon a new trigger flash command (coming from either the I2C or from the TRGFL pin). Figure 19. Typical Flash Pulses with Photo Sense Engaged VSD +VBat VSB D1 PHOTO PHSEN R R/2 GAIN GND U1 R1 22k R/8 Digital Gain Adjust R/4 R/2 R 2R 4R 8R GND I2C R +VREF I2C Comparator Digital Setup U1 STOP Figure 20. Basic Photo Sense Structure On the other hand, the VSD bias voltage is activated when either the charge pump is active, or the ENPH bit in the CONFIG0 register is High. In order to minimize the influence of voltage offset, operating the Photo Sense trigger level in the 360 mV to 1500 mV range is recommended. Picture Light The Picture Light current share the same internal current mirror used to support the Torch/ Video function. The level of current is controlled by the TILED register. In addition, a 200 ms time out is automatically activated when the TILED current is higher than 100 mA. On the other hand, http://onsemi.com 21 NCP5680 the 200 ms time out can be activated by forcing the TPLGT bit to high in the CONFIG0 register. The Picture Light cannot be combined with a power flash pulse. NTC Sensor or by pulsed Hi/Lo the NTCREG[CNTC] bit. In both case, the NTC temperature must be cool enough to enable the power current flow into the LED. Time Out Security The external NTC element is controlled by the ENTC bit in the CONFIG0 register. When the function is activated, the external NTC element is biased by a programmable constant current (in the 10 mA to 630 mA range), the voltage developed across the NTC pin and GND being compared to the reference voltage stored into the NTCREG register. When the NTC voltage drops below the minimum level (setup by the NTCREG register), the charge is de-activated and both the flash and the torch mode are automatically switched OFF, reducing the power dissipated into the LED to almost zero. The associated flip flop is reset to the normal mode when a power OFF/ON sequence is forced, DSTM1 S1 Implementation = /POR 12 13 U4D 74HC132 1 2 When an extra security is requested by the end application, and external structure shall be implemented to handle the worst but rare case condition, i.e. when the NCP5680 built-in timer and time out fail simultaneously. To handle such conditions, an external circuit will switch off the two NMOS transistor when the time extend the maximum 200 ms time out defined by the passive component. There is no software associated with the security circuit, the activation being automatically done when any of the two NMOS is used to generate a power flash pulse. The typical circuit is depicted in Figure 21. 74HC132 U4A 3 U3A 74HC08 3 1 2 DSTM2 S1 Implementation = NMOS C1 1n R1 100k 11 Run V 4 TimeMax 5 U4B Time-Out 6 V 74HC132 V 8 9 U4C 74HC132 10 C2 100n R2 1000k D1 D1N4148 Figure 21. Basic External Hardware Time Out Security Circuit The NMOS signal is derived from the gate drive voltage applied to the external NMOS transistor: this signal is fully synchronized with a photo flash pulse. The positive going slope generates a negative pulse at the RESET input of the flip flop built with two NAND gate which, in turn, activates the delay built with the RC network connected to a single inverter. The flip-flop is set when the RC timing ends (a negative going pulse is present at the SET input), turning ON the external NMOS transistor which, in turn, will force to ground the gate of the power transistor. At this point, the ILED current is disconnected and no more power is dissipated in the circuit. To flip flop is reset by sending a new photo flash sequence, or using any kind of MCU controlled signal. I2C Protocol The NCP5680 is considered as a Slave system, with no possibility to take control of the bus, programmed by means of the standard I2C protocol driven by the external MCU. In addition, the internal STATUS register can be read back upon request coming from the external MCU. To program one particular register, the communication takes place with three serial bytes: http://onsemi.com 22 NCP5680 - Byte#1 physical I2C address = %0111 1100 (Write) / %0111 1101 (Read) - Byte#2 select the internal register to read B7 0 B6 1 BYTE#1 SCL SDA Start NCP5680 address = $7C NCP5680 Function Selection Function = $71 -> Set Up LED1 ILED ILED = 1000mA DATA applies to the selected register I2C transmit completed B5 1 B4 1 BYTE#2 - Byte#3 Data stored into the selected register. Note: the STATUS register is Read only and no byte can be stored from the I2C port into this register. Table 6. I2C Physical address byte (first byte is $7C if Write or $7D is Read) B3 1 B2 1 B1 0 BYTE#3 B0 R/W B7 B6 B5 B4 B3 B2 B1 B0 ACK B7 B6 B5 B4 B3 B2 B1 B0 ACK B7 B6 B5 B4 B3 B2 B1 B0 ACK Read/Write bit = Low -> Write Data = High -> Write Data NCP5680 returns ACK ACK = Low -> byte accepted Figure 22. Typical I2C programming Sequence Example: select the NCP5680 interface ($7C), then select LED1 output current register, then send the value to be stored into the LED1 register. To read the STATUS register, the protocol is slightly different and five I2C cycles are necessary: - Byte#1 physical I2C address = %0111 1100 (Write) to write the STATUS register - Byte#2 select the STATUS register to read = $17 - Byte#3 send an irrelevant data byte ($FF) - Force a STOP condition - Force a START condition - Byte#4 physical I2C address = %0111 1101 (Read) to read the STATUS register - Byte#5 the NCP5680 returns the STATUS contain on the SDA line. The MCU must maintain the SCL signal active. LED Checking Function Although the power transistors are external to the NCP5680 chip, provisions have been made, at silicon level, to protect the system against fault developed during operation. The first element, in regard to the power flash, is an automatic time out sequence engaged when a flash is activated. Such protection will automatically switch off the output current if the pulse width exceeds the time out limit (maximum 255 ms). Similarly, the time out function is automatically de-activated when the Torch/Video mode of operation is selected by software. In this case, the continuous current is limited to 100 mA maximum per LED. Beside the thermal shutdown procedure embedded into the silicon, the second protection feature is the Vout to Ground short circuit protection: the output current is automatically reduced to 60 mA typical, (100 mA max) when such a short is developed across the output voltage pin and ground. According to the power LED manufacturers, an Anode to Cathode short might develop in case of failure: such a situation is detected by the NCP5680 and the associated current loop is automatically disconnected. The test procedure shall be launched by forcing the CKPRC bit in the CONFIG0 register and the procedure is activated upon the positive going slope of this bit. During the check, a 1 mA / 20 ms width typical bias current is forced through the LED. To send a new check sequence, the CKPRC bit must be forced back to low and a new positive edge can be sensed by forcing CKPRC high. Finally, the system permanently monitor the Drain/ Ground voltage of each external NMOS to detect any fault condition in the power flash circuit. A specific command shall be send by the I2C to check the circuit without any on going sequence. The system makes sure the LED is connected to the Vds pin and that no short circuit exist between Vout and Vds (no A/K short-circuit). Such a command over ride the BKL1 and BKL2 status and the check is carried out even when the BKL1 & BKL2 bits are low. In case of failure, the chip de-activate the offender pin and returns the fault bit into the register. The MCU can read the STATUS register content by means of the I2C protocol. http://onsemi.com 23 NCP5680 Figure 23. Basic I2C Read Sequence to Extract the STATUS Register Thermal Shutdown Basic I/O Protection Structure When the thermal shutdown is engaged, the charge pump is fully de-activated and neither the torch/video, nor the flash can be launched. The rest of the chip is maintained active in order to keep a full control of the operation, in particular the SuperCAP bias voltage is active and regulated. +Vcc All the pins of the NCP5680 device are ESD protected by built in diode structure as depicted in Figure 24. Since a diode is attached between the I/O pin and the supply pin, the voltage at the I/O pin shall not extend the VCC voltage plus one Vf drop. Vsw pin D1 I/O Pin D2 FET_N High Voltage Structure FET_P DRIVER FET_N GND D1 Vz45V GND GND Figure 24. Typical ESD Pin Protection Structure Figure 25. Basic ESD Protection Dedicated to Power Pin. Different structures might apply to protect specific pins, in particular the power related functions. In this case, a single diode based clamp structure can be wired to sustain the ESD specifications as depicted in Figure 25. http://onsemi.com 24 NCP5680 Typical Application Schematic Diagram +Vbat C1 GND 10uF 24 TRIG SCL SDA 5 3 4 1 C2 0.22uF C3 0.22uF 21 20 23 22 C1P C1N C2P C2N Vbat TRIGFL SCL SDA VSD Vout 19 C5 + 2 3 - 1 17 IsSCH 16 VgsSCH SCAP 15 Vbias 14 Vds1 Vgs1 Is1 Vds2 10 12 11 9 GND D1 Q2 PWF3 NTLJS4114 R4 GND 0.10R D2 PWF3 Q3 NTLJS4114 R5 GND 0.10R GND 2 6 PHSEN GND NTC 8 Vgs2 13 AGND Is2 7 PGND 18 U1 NCP5680 Figure 26. Basic Power Flash Application +Vbat C1 GND 10uF C2 0.22uF 24 TRIG SCL SDA PHOTO SENSE Q1 100k R2 GND GND NTC GND 5 3 4 1 C4 C3 GND 0.22uF 100uF C2N C2P 23 22 21 20 Vout 19 C1N C1P PVbat IsSCH 17 VgsSCH 16 TRIGFL SCAP 15 SCL Vbias 14 SDA Vds1 10 VSD Vgs1 12 Is1 11 Vds2 9 Vgs2 8 Is2 7 AUXILIARIES R1 0.5R NTGS3433 Q4 2 C5 + 3 - 1 GND D1 NTLJS4114 Q2 R4 PWF3 GND D2 2 PHSEN 6 NTC 13 AGND PGND 18 0.10R NTLJS4114 Q3 R5 0.10R PWF3 GND U1 NCP5680 Figure 27. Full Functions Typical Application http://onsemi.com 25 NCP5680 +Vbat C1 GND 10uF 0.22uF 0.22uF C2 C3 5621 Vout R1 IsSCH 0.5R VGSSCH SCAP Vbias Vds1 4 Q1 NTGS3433 2 1.0Farad 3 3 + C4 - PWF4 1 D1 SCL SDA GND C2P C2N 23 22 21 20 19 Vout C1P C1N 24 IsSCH 17 PVbat VgsSCH 16 5 TRIGFL SCAP 15 SCL 3 SCL Vbias 14 SDA 4 SDA Vds1 10 1 VSD PWF4 D2 D3 PWF4 D4 PWF4 GND 2 PHSEN NTC 6 NTC R2 NTC GND 18 GND 13 AGND PGND Vgs1 Vgs1 12 11 Is1 Is1 Vds2 9 Vds2 Q2A 6 NTLJD4116 21 0.1R R3 Q2B 3 NTLJD4116 5 4 R4 0.1R Vgs2 8 Is2 7 Vgs2 Is2 GND GND U1 NCP5680 Q3A 6 NTLJD4116 NTLJD4116 3 Q3B 21 5 4 0.1R R5 R6 0.1R Figure 28. Typical Quadruple Power LED Capability GND GND http://onsemi.com 26 NCP5680 PACKAGE DIMENSIONS UQFN24 3.5x3.5, 0.4P CASE 523AG-01 ISSUE O D PIN ONE REFERENCE A B 2X E NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e L K MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.15 0.25 3.50 BSC 2.10 2.30 3.50 BSC 2.10 2.30 0.40 BSC 0.30 0.50 0.20 --- 0.15 C 2X 0.15 C 0.10 C 0.08 C NOTE 4 24X L 7 6 24X K ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your loca Sales Representative III III TOP VIEW A1 SIDE VIEW D2 13 1 A3 A C SEATING PLANE SOLDERING FOOTPRINT* 3.90 E2 2.30 1 24X e e/2 24 19 b 0.10 C A B 0.05 C NOTE 3 24X BOTTOM VIEW 0.24 3.90 2.30 24X 0.65 0.40 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 27 NCP5680/D |
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